//--------------------------------------------------------------------------------------------
//
//      Component name  : fpadd_stage1
//      Author          : 
//      Company         : 
//
//      Description     : 
//
//
//--------------------------------------------------------------------------------------------


module FPadd_stage1(ADD_SUB, FP_A, FP_B, clk, ADD_SUB_out, A_EXP, A_SIGN, A_in, A_isINF, A_isNaN, A_isZ, B_EXP, B_XSIGN, B_in, B_isINF, B_isNaN, B_isZ, EXP_diff, cin_sub);
   input         ADD_SUB;
   input [31:0]  FP_A;
   input [31:0]  FP_B;
   input         clk;
   output        ADD_SUB_out;
   reg           ADD_SUB_out;
   output [7:0]  A_EXP;
   reg [7:0]     A_EXP;
   output        A_SIGN;
   reg           A_SIGN;
   output [28:0] A_in;
   reg [28:0]    A_in;
   output        A_isINF;
   reg           A_isINF;
   output        A_isNaN;
   reg           A_isNaN;
   output        A_isZ;
   reg           A_isZ;
   output [7:0]  B_EXP;
   reg [7:0]     B_EXP;
   output        B_XSIGN;
   reg           B_XSIGN;
   output [28:0] B_in;
   reg [28:0]    B_in;
   output        B_isINF;
   reg           B_isINF;
   output        B_isNaN;
   reg           B_isNaN;
   output        B_isZ;
   reg           B_isZ;
   output [8:0]  EXP_diff;
   reg [8:0]     EXP_diff;
   output        cin_sub;
   reg           cin_sub;
   
   
   wire [7:0]    A_EXP_int;
   wire [31:0]   A_SIG;
   wire          A_SIGN_int;
   wire [28:0]   A_in_int;
   wire          A_isDN_int;
   wire          A_isINF_int;
   wire          A_isNaN_int;
   wire          A_isZ_int;
   wire [7:0]    B_EXP_int;
   wire [31:0]   B_SIG;
   wire          B_SIGN_int;
   wire          B_XSIGN_int;
   wire [28:0]   B_in_int;
   wire          B_isDN_int;
   wire          B_isINF_int;
   wire          B_isNaN_int;
   wire          B_isZ_int;
   reg [8:0]     EXP_diff_int;
   wire [8:0]    a_exp_in;
   wire [8:0]    b_exp_in;
   wire          cin_sub_int;
   
   
   always @(posedge clk)
      
      begin
         A_SIGN <= A_SIGN_int;
         B_XSIGN <= B_XSIGN_int;
         A_in <= A_in_int;
         B_in <= B_in_int;
         A_EXP <= A_EXP_int;
         B_EXP <= B_EXP_int;
         EXP_diff <= EXP_diff_int;
         A_isZ <= A_isZ_int;
         B_isZ <= B_isZ_int;
         A_isINF <= A_isINF_int;
         B_isINF <= B_isINF_int;
         A_isNaN <= A_isNaN_int;
         B_isNaN <= B_isNaN_int;
         ADD_SUB_out <= ADD_SUB;
         cin_sub <= cin_sub_int;
      end
   
   assign a_exp_in = {1'b0, A_EXP_int};
   
   assign b_exp_in = {1'b0, B_EXP_int};
   
   assign cin_sub_int = (A_isZ_int | A_isDN_int) ^ (B_isZ_int | B_isDN_int);
   
   assign A_in_int = {2'b00, A_SIG[23:0], 3'b000};
   
   assign B_in_int = {2'b00, B_SIG[23:0], 3'b000};
   
   
   reg [9:0]     mw_I5t0;
      reg [9:0]     mw_I5t1;
      reg [9:0]     diff;
      reg           borrow;

   always @(a_exp_in or b_exp_in or cin_sub_int)
   begin: I5combo
      
      mw_I5t0 = {a_exp_in[8], a_exp_in};
      mw_I5t1 = {b_exp_in[8], b_exp_in};
      borrow = cin_sub_int;
      diff = $signed(mw_I5t0) - $signed(mw_I5t1) - borrow;
      EXP_diff_int = (diff[8:0]);
   end
   
   assign B_XSIGN_int = (~(B_SIGN_int ^ ADD_SUB));
   
   
   UnpackFP I1(.FP(FP_A), .SIG(A_SIG), .EXP(A_EXP_int), .SIGN(A_SIGN_int), .isNaN(A_isNaN_int), .isINF(A_isINF_int), .isZ(A_isZ_int), .isDN(A_isDN_int));
   
   UnpackFP I3(.FP(FP_B), .SIG(B_SIG), .EXP(B_EXP_int), .SIGN(B_SIGN_int), .isNaN(B_isNaN_int), .isINF(B_isINF_int), .isZ(B_isZ_int), .isDN(B_isDN_int));
   
endmodule
